The present invention relates to a phase detector used for various types of digital Communications such as satellite communications or mobile communications and capable of realizing rapid timing phase synchronization within a preamble and low phase-timing jitter in a data section and also capable of promoting reduction of a size and a weight of a device. This invention also relates to a timing recovery device which uses the phase detector, and a demodulator which uses the timing recovery device.
As a timing recovery device in a demodulator for digital radio communications based on the conventional technology, there is a feedback type of device which detects advance or delay in phase from the information on the absolute value of phase data whose difference has been taken as described in the reference xe2x80x9cTiming Recovery Scheme Using Received Signal Phase Information for QPSK Modulationxe2x80x9d (by Fujimura, in Proceedings of Electronic Information Communication Association, Vol. J81-B-II No. 6, pp.665-668, June, 1998).
FIG. 22 is a block diagram showing a general configuration of a receiver containing a demodulator having a timing recovery device based on the conventional technology. As shown in FIG. 22, an antenna 101 receives RF signal containing a QPSK demodulation signal, and a frequency converting section 102 outputs a baseband signal comprising an in-phase component and an orthogonal component by successively subjecting this RF signal to amplification, band restriction, and frequency conversion.
A/D converter 111a samples the in-phase component and an A/D converter 1116 samples the orthogonal component of the baseband signal at each time t=xcfx84+iT/2. The A/D converter 111a outputs the sampled data array Ii (in-phase amplitude component) and while the A/D converter 111b outputs sampled data array Qi (orthogonal amplitude component). Herein T indicates a symbol duration and xcfx84 indicates a timing error in a range of xe2x88x92T/2xe2x89xa6xcfx84xe2x89xa62. Here i is a natural number such as 1, 2, 3 . . . It should be noted that sampling of a baseband signal by the A/D converters 111a, 111b is executed in a first transitional edge of a sampling clock SSK outputted from a timing recovery section 112 described later.
A coordinate transform section 110 computes a baseband signal phase data array xcex8i by executing coordinate transformation, namely inverse tangent computing using the data array Ii and Qi outputted from the A/D converters 111a, 111b respectively.
xe2x80x83xcex8i=tanxe2x88x921.(Qi/Ii)xe2x80x83xe2x80x83(1)
A timing recovery section 112 executes phase control, namely timing recovery processing for generating a sampling clock SSK and a recovered symbol clock RRC each phase-synchronized with the inputted baseband signal using the phase data array xcex8i outputted from the coordinate transform section 110.
Nyquist data extracting section 113 extracts a data array at an Nyquist point using the recovered symbol clock RRC from the data arrays Ii and Qi sampled with the sampling clock SSK. A data determining section 116 determines data according to the data arrays at the Nyquist point, and outputs the data as demodulated data to a decoder 104. The decoder 104 executes decode processing according to the demodulated data. It should be noted that data determination by the data determining section 116 is executed based on a coherent detection scheme or a differential detecting scheme compatible with the modulating system.
Herein detailed description is made for the timing recovery processing by the timing recovery section 112 by referring to FIG. 23 to FIG. 25A. Herein description is made for a case when a bust signal comprising a preamble section used for timing recovery or the like and a data section including a message as a random pattern is received. FIG. 23 is a view showing temporal change in the phase xcex8(t) of a baseband signal when a 0xcfx80 demodulated signal repeating a phase fluctuation of xc2x1180 (degree) for one symbol is received and a temporal change in the absolute signal xcex1(t) of deviation for T/2 of this phase xcex8(t) (xc2xd of symbol duration). FIG. 24 is a view showing a temporal change in the phase xcex8(t) of the baseband signal when a random pattern of a data section in which the phase xcex8(t) changes at random is received and a temporal change of an absolute signal xcex1(t) of deviation for T/2 of this phase xcex8(t). FIG. 25A and FIG. 25B are constellation views showing amplitude shift of a baseband signal at a Nyquist point. In these figures the horizontal axis indicates an in-phase component (I channel) of a baseband signal, while the vertical axis indicates an orthogonal component (Q channel) of the baseband signal. FIG. 25A is a constellation view showing a state when there is no DC offset, and FIG. 25B is a constellation view showing a state where DC offset is added.
The preamble signal shown in FIG. 23 is a signal alternately shifting at the point A or the point C in FIG. 25A, while the random pattern signal shown in FIG. 24 is a signal shifting at random at any point between the points A and D in FIG. 25A. In otherwords, the phase xcex8(t) of the preamble signal shown in FIG. 23 repeats fluctuation of 180 degrees in one symbol duration, and the xcex8(t) of the random pattern signal shown in FIG. 24 repeats fluctuations of 0, xc2x190, xc2x1180 degrees in one symbol duration. It should be noted that the time t=0, T, 2T, 3T, . . . on the time axis indicates a Nyquist point, and that t=0 indicates arrival of the first burst signal. T indicates a symbol duration.
An absolute value signal xcex1(t) of a deviation of T/2 time is defined by the following equation (2).
xcex1(t)=min [|xcex8(t)xe2x88x92xcex8(txe2x88x92T/2)|, 360xe2x88x92|xcex8(t)xe2x88x92xcex8(txe2x88x92T/2)|]xe2x80x83xe2x80x83(2)
This absolute value signal xcex1(t) is a signal obtained based on the fact that the change in the phase xcex8(t) is rather moderate around the Nyquist point (t=0, T, 2T, 3T, . . . ) and is sharp around points at T/2 symbol time after the Nyquist point (t=T/2, 3T/2, 5T/2, 7T/2, . . . ). The absolute value signal xcex1(t) shown in FIG. 23 and FIG. 24 includes a symbol frequency component s(t) and a DC component as shown in the following equation (3) whether or not the signal is a preamble signal or a random pattern signal. Namely, the signal xcex1(t) includes a symbol frequency component
s(t)=xe2x88x92sin 2xcfx80t/Txe2x80x83xe2x80x83(3)
and a DC component. Especially, when a preamble signal is received, lot of symbol frequency components s(t) are included in the signal xcex1(t).
Herein a difference signal xcex94xcex1(t) for the absolute value signal xcex1(t) with xc2xd symbol time interval is defined as indicated by the following equation:
xcex94xcex1(t)=xcex1(t)xe2x88x92xcex1(txe2x88x92T/2)xe2x80x83xe2x80x83(4)
Following relation exists between an average value M[xcex94xcex1(ta)] of this difference signal xcex94xcex1(t) at the time ta=xcfx84+jT and the timing error xcfx84. Herein, j is a natural number such as 1, 2, 3 . . .
when M[xcex94xcex1(ta)] less than 0 then 0 less than xcfx84 less than T/2
when M[xcex94xcex1(ta)] greater than 0 then xe2x88x92T/2 less than xcfx84 less than 0xe2x80x83xe2x80x83(5)
It should be noted that, when M[xcex94xcex1(ta)] is equal to zero, xcfx84 is also equal to zero.
Similarly the following relation as expressed by the equation (6) exists between the average value [xcex94xcex1(t)xc3x97(xe2x88x921)i] of values each obtained by multiplying the difference signal xcex94xcex1(t) at the time tb=xcfx84+iT/2 and the timing error xcfx84:
when M[xcex94xcex1(tb)xc3x97(xe2x88x921)i] less than 0 then 0 less than xcfx84 less than T/2
when M[xcex94xcex1(tb)xc3x97(xe2x88x921)i] greater than 0 then xe2x88x92T/2 less than xcfx84 less than 0xe2x80x83xe2x80x83(6)
It should be noted that when M[xcex94xcex1(tb)xc3x97(xe2x88x921)i] is equal to zero, xcfx84 is also equal to zero.
Accordingly, timing synchronicity with a baseband signal can be established by controlling a phase of the sample timing SSK according to information on the average value M[xcex94xcex1(ta)] or the average value M[xcex94xcex1(tb)xc3x97(xe2x88x921)i], namely according to information including a symbol frequency component and providing feedback controls so that the value of the average value M[xcex94xcex1(ta)] or the average value M[xcex94xcex1(tb)xc3x97(xe2x88x921)i] is convoluted to 0.
Actual controls over this timing synchronicity is executed by an equal timing recovery section 112, and description is made hereinafter for controls when information on the average value M[xcex94xcex1(tb)xc3x97(xe2x88x921)i] at T/2 time is used.
In FIG. 22, a phase subtracting type of phase detector 121 computes a phase deviation data array ai expressed by the following equation (7) corresponding to the equation (2) according to a phase data array xcex8i outputted from the coordinate transform section 110. Namely, xcex1i is computed through the following equation:
xcex1i=min [|xcex8ixe2x88x92xcex8ixe2x88x921|, 360xe2x88x92|xcex8ixe2x88x92xcex8ixe2x88x921|]xe2x80x83xe2x80x83(7)
Herein i is an integer (i=0, xc2x11, xc2x12, xc2x13, . . . ).
Further, the phase subtracting type of phase detector 121 computes a phase detection data array as expressed by the following equation (8) corresponding to the equation (4) according to the phase deviation data array xcex1i. Namely, the xcex4i is computed through the following equation:
xcex4i=(xcex1ixe2x88x92xcex1ixe2x88x921)xc3x97(xe2x88x921)ixe2x80x83xe2x80x83(8)
Herein i is an integer (i=0, xc2x11, xc2x12, xc2x13, . . . ).
An averaging section 122 comprises a random walk filter. The averaging section 122 averages the phase detection data array xcex4i outputted from the phase subtracting type of phase detector 121 and outputs a control signal Vixcex5[1, 0, xe2x88x921]. Namely, the averaging section 122 outputs the control signal Vi=1 when an average value of the phase detection data array xcex4i is positive, outputs the control signal Vi=xe2x88x921 when the average value is negative, and outputs the control signal Vi =0 when the average value of the phase detection data array xcex4i is zero.
A phase controller 123 controls the phase of the sampling clock SSK outputted from this phase controller 123 according to the control signal Vi outputted from the averaging section 122. Namely, the phase control section 123 delays the sampling clock SSK when the control signal Vi=1 is inputted, advances the sampling clock SSK when the control signal Vi=xe2x88x921 is inputted, and maintains the sampling clock SSK as it is when the control signal Vi=0 is inputted. This phase-controlled sampling clock SSK is used as a sampling clock by the A/D converters 111a, 111b. It should be noted that step width of phase control by the phase control section 123 is, for instance, T/16 ({fraction (1/16)} of the symbol duration).
Further, a dichotomizer 124 dichotomizes the sampling clock SSK phase-controlled by the phase control section 123. The dichotomizer 124 outputs the dichotomized signal as a recovered symbol clock RRC and this recovered symbol clock RRS is used for latching a Nyquist point in the Nyquist data extracting section 113. The recovered symbol clock RRS is also used as a clock for the decoder 104.
In recent years, however, to achieve reduction in size and weight of a decoder, hot attention is being drawn on a direct conversion system in which a baseband signal is obtained by directly multiplying a radio frequency signal (RF signal) by a local frequency signal which is the same as this radio frequency signal. When this direct conversion system is used, there is a problem that a DC offset is added to the baseband signal and hence the BER (bit error rate) is substantially degraded.
To solve this problem, for instance, in Japanese Patent Laid-Open Publication No. HEI 6-261088, there is described a decoder offset removing circuit in which a baseband signal is inputted into a low-pass filter where the a DC offset component is detected and this detected DC offset component is removed by correction from the baseband signal.
FIG. 26 is a block diagram showing configuration of a receiver based on the conventional technology in which a mechanism for removing the DC offset is added to the demodulator in the receiver shown in FIG. 22. Namely, the receiver shown in FIG. 26 comprises an offset detector 131 and an offset correcting section 132 provided between the A/D converters 111a, 111b and the coordinate transform section 110 in the receiver shown in FIG. 22.
The offset detector 131 inputs data arrays Ik, Qk outputted from the A/D converters 111a, 111b into a low-pass filter and detects DC offset components ID, QD respectively. When the low-pass filter has an moving average circuit, the moving average is detected as DC offset components ID, QD. The DC offset component ID is the DC offset component corresponding to the data array Ik, and the DC offset component QD is a DC offset component corresponding to the data array Qk.
The offset correcting section 132 subtracts the DC offset components ID, QD outputted from the offset detector 131 from data arrays Ik, Qk respectively to correct the data arrays each with a DC offset component having been removed therefrom, and outputs the corrected data to the coordinate transform section 110.
With the conventional type of demodulator for a receiver as described above, it is possible to remove a DC offset component, however, until this DC offset component is removed to some extent by the offset correcting section 132, timing synchronicity can not be established by the timing recovery section 112. A time required until the timing synchronicity is established and demodulation can be executed is equal to a sum of the time after a header section of data indicated by a baseband signal is inputted until the DC offset is removed and the time after the DC offset is removed to some extent until timing phase synchronization is completed. Since a longer time is required to remove the DC offset a long time is disadvantageously required after a header of data is inputted into the demodulating section until data is normally demodulated.
When this DC offset is not removed demodulation of data can not be performed correctly. A state in which data can not be demodulated correctly is explained here. When the DC offset is still appended to data the points A to D on the constellation view shown in FIG. 25B are shifted in the direction of the first quadrant.
FIG. 27 is a view showing a temporal change in the phase xcex8(t) when a preamble is received in the state when the DC offset is still appended and a temporal change in the absolute value signal xcex1(t) for a deviation of this phase xcex8(t) for T/2 time. As described above, when a preamble is received, the phase is shifted at the point A to point D alternately on the constellation diagram in FIG. 25B. Accordingly, the phase xcex8(t) when receiving a preamble does not repeat between the phase 45 degrees and the phase 225 degrees in a state when DC offset is not present, and always have a value around the phase 45 degrees. Namely, the phase xcex8(t) changes little. Therefore, even if the absolute value signal xcex1(t) is computed, because the phase xcex8(t) itself does not change, much the absolute value signal xcex1(t) also does not change much and the value is close to zero. As a result, a symbol frequency component s(t) is not present in the absolute value signal xcex1(t) at all.
On the other hand, FIG. 28 is a view showing a temporal change in the phase xcex8(t) when a random pattern is received in the state where DC offset is still offset, and a historical change of the absolute value signal xcex1(t) for a deviation of this xcex8(t) for T/2 time. When a random pattern is being received, the phase shifts between the points A to D on the constellation diagram shown in FIG. 25B randomly. When a random pattern is being received, the phase xcex8(t) only shifts among the phase 0 degree, phase 45 degree and phase 90 degree, and as compared to a case where DC offset is not present, the phase change is drastically reduced. Further, even if the absolute value signal xcex1(t) is computed, as a deviation of the phase xcex8(t) itself becomes smaller, so that a section in which the symbol frequency component s(t) in the absolute value signal xcex1(t) becomes substantially smaller. A percentage of a symbol frequency component s(t) included in this absolute value signal xcex1(t) becomes smaller as the DC offset increases.
As a timing phase corresponding to a symbol frequency can not be detected in the state where a DC offset is included as described above, advance or delay in the timing phase of the baseband signal can not be detected, which makes it impossible to establish timing synchronicity, and also a period of time until this DC offset is removed is added as a period of time required until the timing synchronicity is established.
Further, the demodulator 103 based on the conventional technology as described above requires a mechanism for computing a data array xcex8i by using the coordinate transforming section 110. Because a volume of operations for this coordinate transformation is large, a long period of time is required for demodulation processing, which in turn requires a long period of time until a timing synchronicity is established. Even if this coordinate transformation is executed by using a ROM, a scale of the transform circuit can not be ignored, and as a result a scale of a demodulator or that of the entire receiver becomes disadvantageously large.
The demodulator 103 for a receiver based on the conventional technology as described above generally executes feedback processing by using a PLL (phase Synchronicity Loop) type of synchronizing circuit. Because a time delay due to a register in a loop in this PLL is shorter, the characteristics of more rapid timing phase synchronization and low phase jitter can be realized. However, as the coordinate transform section 110 which executes a vast amount of calculations is present inside the PLL loop, a time delay in the PLL loop tends to become larger, and timing phase synchronization in the subsequent steps and phase jitter disadvantageously degrade the characteristics.
To solve the problems as described above, it is an object of the present invention to provide a phase detector capable of detecting a timing phase of a baseband signal regardless of whether DC offset is included in the baseband signal or not, execution demodulation by executing the timing phase adjustment using this detected timing phase, and realizing rapid timing phase synchronization and low phase jitter with simple computing processing as well as simple configuration, a timing recovery device using this phase detector, and also a demodulator using this timing recovery device.
It is another object of the present invention to provide a phase detector capable of detecting a timing phase by means of simple addition and subtraction using information on a baseband signal having an amplitude restricted into a specified range with a limiter amplifier, executing demodulation processing by executing timing phase adjustment using this detected timing phase, and also realizing rapid timing phase synchronization and low phase jitter with simple computing processing as well as with simple configuration, a timing recovery device using this phase detector, and a demodulator using this timing recovery device.
It is still another object of the present invention to provide a phase detector capable of shortening a period of time until a baseband signal is normally demodulated by executing removal of DC offset and timing phase synchronization concurrently, a timing recovery device using this phase detector, and a demodulator using this timing recovery device.
With the present invention, a in-phase amplitude deviation computing unit computes in-phase amplitude deviation which is an absolute value of a value obtained when the inphase amplitude components at 1/n (where n is a natural number greater than 1) of a symbol duration of a baseband signal are subtracted from each other; a orthogonal amplitude deviation computing unit computes orthogonal amplitude deviation which is an absolute value of a value obtained when the orthogonal amplitude components at 1/n (where n is a natural number greater than 1) of a symbol duration of a baseband signal are subtracted from each other; and a synthesized amplitude deviation computing unit computes a synthesized amplitude deviation obtained by adding the in-phase amplitude deviation and the orthogonal amplitude deviation; and a timing phase of the baseband signal is detected according to the synthesized amplitude deviation. Therefore, timing phase can be detected with simple configuration. Further, the synthesized amplitude deviation is obtained through simple addition or subtraction between an in-phase amplitude component and an orthogonal amplitude component, so that high speed processing and size and weight reduction of a mechanism for detecting phase can be realized.
With the present invention, a difference value computing unit computes a difference between the synthesized amplitude deviations at xc2xd symbol time; and a phase detection signal indicating detection of advance or delay in the timing phase of the baseband signal is outputted according to the difference. Therefore, even if a DC offset is included in the baseband signal or the amplitude of the baseband signal is limited into a specified range with a limiter amplifier or the like, a timing phase for the baseband signal can accurately be detected.
With the present invention, the synthesized amplitude deviation computing unit outputs a value obtained by adding a square of the in-phase amplitude deviation to a square of the orthogonal amplitude deviation as the synthesized amplitude deviation. Therefore, more precise synthesized amplitude deviation can be obtained and also timing phase detection can be executed with high precision.
With the present invention, the synthesized amplitude deviation computing unit outputs a square root of a value obtained by adding a square of the in-phase amplitude deviation to the orthogonal amplitude deviation as the synthesized amplitude deviation. Therefore, more precise synthesized amplitude deviation can be obtained and timing phase detection can be made with higher precision.
With the present invention, a first weightage unit computes an in-phase amplitude symbol time deviation which is an absolute value of a value obtained when the in-phase amplitude components at symbol duration time of a baseband signal are subtracted from each other, and provides a weightage to the in-phase amplitude deviation using the computed in-phase amplitude symbol time deviation; and a second weightage unit computes an orthogonal amplitude symbol time deviation which is an absolute value of a value obtained when the orthogonal amplitude components at symbol cycle time of a baseband signal are subtracted from each other, and provides a weightage to the orthogonal amplitude deviation using the computed orthogonal amplitude symbol time deviation. Therefore, more precise timing phase detection can be executed and more rapid timing phase synchronization and reduction of phase jitter can be promoted.
With the present invention, a first signal shift amount computing unit computes an in-phase amplitude symbol time deviation which is an absolute value of a value obtained when the in-phase amplitude components at symbol cycle time of a baseband signal are subtracted from each other; a second signal shift amount computing unit computes an orthogonal amplitude symbol time deviation which is an absolute value of a value obtained when the orthogonal amplitude components at symbol cycle time of a baseband signal are subtracted from each other; a shift determining unit determines whether the in-phase amplitude symbol time deviation and the orthogonal amplitude symbol time deviation have a value which is less than a specified value or not; and an inverting unit inverts the phase detection signal when it is determined by the shift determining unit that the in-phase amplitude symbol time deviation and the orthogonal amplitude symbol time deviation have a value which is less than the specified value and outputting this inverted phase detection signal. Therefore, timing phase can be detected more precisely and rapid timing phase synchronization and reduction of phase jitter can be realized.
With the present invention, a first multiplying unit generates a cosine multiplication signal by multiplying the synthesized amplitude deviation by cosine of the free symbol frequency signal; a second multiplying unit generates a sine multiplication signal by multiplying the synthesized amplitude deviation by sine of the free symbol frequency signal; and a timing difference computing unit computes a inverse tangent of the sine multiplication signal against the cosine multiplication signal and outputting the inverse tangent as a timing phase for the free symbol frequency signal against the baseband signal. Therefore, timing phase can be detected under stable conditions regardless of an initial timing phase value.
With the present invention, a phase detecting unit outputs a phase detection signal indicating advance or delay in the timing phase of the baseband signal from a difference of a synthesized amplitude deviation at xc2xd of a symbol duration, which synthesized amplitude deviation is obtained by adding an in-phase amplitude deviation which is an absolute value of a value obtained when the in-phase amplitude components at xc2xd of a symbol duration of a baseband signal sampled at a sampling clock that is two times faster than a symbol rate are subtracted from each other to an orthogonal amplitude deviation which is an absolute value of a value obtained when the orthogonal amplitude components at xc2xd of a symbol duration of the baseband signal are subtracted from each other; an averaging unit outputs an average value of phase detection signals outputted from the phase detecting unit as a phase control signal; a phase control unit provides phase control over the sampling clock according to the phase control signal outputted from the averaging unit; and a dichotomizing unit dichotomizes the sampling clock having been subjected to phase control by the phase control unit and outputs this dichotomized clock as a recovered symbol clock. Therefore, regardless of whether a DC offset is present in a baseband signal or an amplitude of a baseband signal is limited or not, rapid timing phase synchronization when receiving a preamble and low phase jitter when receiving a random pattern in a data section can be realized. A synthesized amplitude deviation can be obtained with simple addition or subtraction, so that it is possible to minimize a circuit scale and further promote downsizing. Further, a delay time within a PLL feedback group can be made smaller which enables high speed processing. Further, the phase detecting unit operates by using information on in-phase and orthogonal amplitudes of a baseband signal sampled two times higher than the symbol rate, so that a operating speed two times higher than the symbol rate can be realized and the phase detecting unit can easily be applied to a high speed radio communication system for multimedia with the symbol rate of several tens MHz or more.
With the present invention, a phase detecting unit computes a value obtained by adding a square of the in-phase amplitude deviation to a square of the orthogonal amplitude deviation as the synthesized amplitude deviation. Therefore, timing phase can be detected more precisely and as a result rapid timing phase synchronization and low phase jitter can be realized.
With the present invention, a phase detecting unit computes a square root of a value obtained by adding a square of the in-phase amplitude deviation to a square of the orthogonal amplitude deviation as the synthesized amplitude deviation. Therefore, timing phase can be detected more precisely and as a result rapid timing phase synchronization and low phase jitter can be realized.
With the present invention, a first weightage unit computes an in-phase amplitude symbol time deviation which is an absolute value of a value obtained when the in-phase amplitude components at symbol cycle time of a baseband signal are subtracted from each other, and provides a weightage to the in-phase amplitude deviation using the computed in-phase amplitude symbol time deviation; and a second weightage unit computes an orthogonal amplitude symbol time deviation which is an absolute value of a value obtained when the orthogonal amplitude components at symbol cycle time of a baseband signal are subtracted from each other, and provides a weightage to the orthogonal amplitude deviation using the computed orthogonal amplitude symbol time deviation for deleting information when a phase inversion is generated in the symbol frequency component when signal sift does not occur. Therefore, timing phase can be detected more precisely and rapid timing phase synchronization and reduction of phase jitter can be promoted.
With the present invention, a quartering unit quarters a free sampling clock which is four times faster than a symbol rate and outputs this quartered clock as a free symbol clock; a phase detecting unit a) obtains a synthesized amplitude deviation by adding an in-phase amplitude deviation which is an absolute value of a value obtained when the in-phase amplitude components at 1/n (where n is equal to 2 or 4) of a symbol duration of a baseband signal sampled at the free symbol clock are subtracted from each other to an orthogonal amplitude deviation which is an absolute value of a value obtained when the orthogonal amplitude components at 1/n (where n is equal to 2 or 4) of a symbol duration of a baseband signal are subtracted from each other, b) obtains a cosine multiplication signal by multiplying the synthesized amplitude deviation by cosine of a frequency component of the free symbol clock and a sine multiplication signal by multiplying the synthesized amplitude deviation by sine of a frequency component of the free symbol clock, and c) outputs the cosine multiplication signal and the sine multiplication signal as a phase detection signal indicating advance or delay in the timing phase of the baseband signal; an averaging unit outputs a cosine multiplication control signal and a sine multiplication control signal as a phase control signal, which cosine multiplication control signal is the average of the cosine multiplication signal and which sine multiplication control signal is the average of the sine multiplication signal in the phase detection signal outputted by the phase detecting unit; and a clock generating unit computes a timing phase which is a inverse tangent of the cosine multiplication control signal and the sine multiplication control signal of the phase control signals outputted from the averaging unit, and generates a recovered symbol clock by phase-shifting the free symbol clock by the timing phase. Therefore, regardless of whether a DC offset is present in a baseband signal or not or whether the amplitude of the baseband signal is limited or not, rapid timing phase synchronization when receiving a preamble and low phase jitter when receiving a random pattern can be realized. As the synthesized amplitude deviation can be obtained with simple addition and subtraction, so that a circuit scale can be made smaller and downsizing of the device can be promoted. Further, delay time within a PLL feedback loop can be reduced, which enables high speed processing. Further, a recovered symbol clock is generated with a feed forward, so that regardless of the value of the initial timing phase, a time required for timing phase synchronization is decided according to a time constant or the like of a filter in the averaging unit, which enables a stable timing phase synchronization operation.
With the present invention, a phase detecting unit computes a value obtained by adding a square of the in-phase amplitude deviation to a square of the orthogonal amplitude deviation as the synthesized amplitude deviation to obtain a synthesized amplitude deviation with higher precision. Therefore, timing phase can be detected more precisely and as a result rapid timing phase synchronization and low phase jitter can be realized.
With the present invention, phase detecting unit computes a square root of a value obtained by adding a square of the in-phase amplitude deviation to a square of the orthogonal amplitude deviation as the synthesized amplitude deviation to obtain a synthesized amplitude deviation with higher precision. Therefore, timing phase can be detected more precisely, and as a result rapid timing phase synchronization and low phase jitter can be realized.
With the present invention, a first weightage unit computes an in-phase amplitude symbol time deviation which is an absolute value of a value obtained when the in-phase amplitude components at symbol cycle time of a baseband signal are subtracted from each other, and provides a weightage to the in-phase amplitude deviation using the computed in-phase amplitude symbol time deviation; and a second weightage unit computes an orthogonal amplitude symbol time deviation which is an absolute value of a value obtained when the orthogonal amplitude components at symbol cycle time of a baseband signal are subtracted from each other, and provides a weightage to the orthogonal amplitude deviation using the computed orthogonal amplitude symbol time deviation to delete information when phase reversion in the symbol frequency component occurs in a state where signal shift does not occur. Therefore, timing phase can be detected more precisely and rapid timing phase synchronization and reduction of phase jitter can be promoted.
With the present invention, a sampling unit samples a baseband signal with a sampling clock which is two times faster than a symbol rate; a phase detecting unit outputs a phase detection signal indicating advance or delay in the timing phase of the baseband signal from a difference of a synthesized amplitude deviation at xc2xd of a symbol duration, which synthesized amplitude deviation is obtained by adding an in-phase amplitude deviation which is an absolute value of a value obtained when the in-phase amplitude components at xc2xd of a symbol duration of the baseband signal are subtracted from each other to an orthogonal amplitude deviation which is an absolute value of a value obtained when the orthogonal amplitude components at xc2xd of a symbol duration of the baseband signal are subtracted from each other; an averaging unit outputs an average value of phase detection signals outputted from the phase detecting unit as a phase control signal; a phase control unit provides phase controls over a sampling clock used by the sampling unit according to the phase control signal outputted from the averaging unit; a dichotomizing unit dichotomizes the sampling clock phase-controlled by the phase control unit and outputs the dichotomized clock as a recovered symbol clock; a Nyquist point data extracting unit extracts Nyquist point data for the baseband signal sampled by the sampling unit using the recovered symbol clock; an offset detecting unit averages the Nyquist point data extracted by the Nyquist point data extracting unit and detects a DC offset from the average data; a correcting unit corrects the Nyquist point data by subtracting the DC offset detected in the offset detecting unit from the Nyquist point data extracted in the Nyquist point data extracting unit; and a determining unit determines data for the baseband signal according to the Nyquist point data corrected by the correcting unit. Therefore, regardless of whether a DC offset is present in a baseband signal or the amplitude of the baseband signal is limited or not, rapid timing phase synchronization when receiving a preamble and low phase jitter when receiving a random pattern in a data section can be realized and degradation of BER can also be reduced. As a synthesized amplitude deviation can be obtained with simple addition and subtraction, the circuit scale can be made smaller and downsizing of the device can be promoted. Further, as a delay time within a PLL feedback loop can be reduced, high speed processing becomes possible. Further, as the device operates using information on in-phase and orthogonal amplitudes of a baseband signal sampled at a rate two times higher than a symbol rate, so that operation speed two times faster than the symbol rate can be realized. Further, the demodulator according to the present invention can easily be applied to a high speed radio communication system for multimedia with the symbol rate of several tens MHz or more. Further, the processing for synchronizing a timing phase and processing for removing DC offset are concurrently executed in the demodulator, so that even when a DC offset is present in the baseband signal, time required until demodulation is correctly executed can be shortened, and as a result the transmission efficiency can be improved.
With the present invention, a free clock unit generates a free sampling clock which is four times faster than a symbol rate; a quartering unit quarters the free sampling clock generated by the free clock unit and outputs the quartered clock as a free symbol clock; a sampling unit samples a baseband signal with the free sampling clock generated by the free clock unit; a phase detecting unit a) obtains a synthesized amplitude deviation by adding an in-phase amplitude deviation which is an absolute value of a value obtained when the in-phase amplitude components at 1/n (where n is equal to 2 or 4) of a symbol duration of a baseband signal sampled at the free symbol clock are subtracted from each other to an orthogonal amplitude deviation which is an absolute value of a value obtained when the orthogonal amplitude components at 1/n (where n is equal to 2 or 4) of a symbol duration of a baseband signal are subtracted from each other, b) obtains a cosine multiplication signal by multiplying the synthesized amplitude deviation by cosine of a frequency component of the free symbol clock and a sine multiplication signal by multiplying the synthesized amplitude deviation by sine of a frequency component of the free symbol clock, and c) outputs the cosine multiplication signal and the sine multiplication signal as a phase detection signal indicating advance or delay in the timing phase of the baseband signal; an averaging unit outputs a cosine multiplication control signal and a sine multiplication control signal as a phase control signal, which cosine multiplication control signal is the average of the cosine multiplication signal and which sine multiplication control signal is the average of the sine multiplication signal in the phase detection signal outputted by the phase detecting unit; a clock generating unit computes a timing phase which is a inverse tangent of the cosine multiplication control signal and the sine multiplication control signal of the phase control signals outputted from the averaging unit, and generates a recovered symbol clock by phase-shifting the free symbol clock by the timing phase; a Nyquist point data extracting unit extracts Nyquist point data for the baseband signal sampled by the sampling unit using the recovered symbol clock; an offset detecting unit averages the Nyquist point data extracted by the Nyquist point data extracting unit and detects a DC offset from the average data; a correcting unit corrects the Nyquist point data by subtracting the DC offset detected in the offset detecting unit from the Nyquist point data extracted in the Nyquist point data extracting unit; and a determining unit determines data for the baseband signal according to the Nyquist point data corrected by the correcting unit. Therefore, regardless of whether a DC offset is present in a baseband signal or the amplitude of the baseband signal is limited or not, rapid timing phase synchronization when receiving a preamble and low phase jitter when receiving a random pattern in a data section can be realized and degradation of BER can be reduced. As a synthesized amplitude deviation can be obtained with simple addition and subtraction, the circuit scale can be made smaller and downsizing of the device can be promoted. Further, as a delay time within a PLL feedback loop can be reduced, high speed processing becomes possible. Further, as the device operates using information on in-phase and orthogonal amplitudes of a baseband signal sampled at a rate two times higher than a symbol rate, so that operation speed two times faster than the symbol rate can be realized. Further, the demodulator according to the present invention can easily be applied to a high speed radio communication system for multimedia with the symbol rate of several tens MHz or more. Further, the processing for synchronizing a timing phase and processing for removing DC offset are concurrently executed in the demodulator, so that even when a DC offset is present in the baseband signal, time required until demodulation is correctly executed can be shortened, and as a result the transmission efficiency can be improved.
Other objects and features of this invention will become apparent from the following description with reference to the accompanying drawings.